65nm Logic Process

The 65nm logic process features multiple transistor options for optimum system level tuning. A feature new to 65nm is the triple gate oxide, which provides hierarchical system-on-a-chip (SOC) design flexibility allowing designers to fully optimize the device based upon power, performance and leakage requirements. With a realizable density improvement of 38% when migrating from 90nm to 65nm, 65nm offers a cost competitive process solution for customers requiring advance process technology with IP design enablements.

The logic process is built on a modular process architecture so modules such as embedded memories, analog/mixed-signal and RFCMOS can be easily incorporated based upon the requirements of the device. This flexibility provides the users an ability to optimize the mask layers to what is actually required by the product without incurring the cost for process options that are not being utilized.

65nm Logic Transistors
65nm Generic (1.0V)	65nm Low Power Enhanced (1.2V)
Standard Vt	Standard Vt
High Vt	High Vt
Low Vt	Low Vt
I/O VDD OPTIONS 3.3, 2.5, 1.8, 1.5, 1.2V	I/O VDD OPTIONS 3.3, 2.5, 1.8V

Process Features

Process Technology	Key Characteristics
Well	Super Steep Retrograde
Isolation	Shallow Trench
Gate	Surface-channel N & PMOS, source/drain extension with pocket implant, triple gate oxide option (Generic)
Lithography	193/248 nm lithography with OPC/PSM
Salicidation	Low resistance Nickel with salicide-block option
Metal Interconnect	Up to 9 layers Dual-Damascene Cu with different Backend-Of-Line option (1x, 2x, 4x metal pitch)
Inter-metal dielectic	Low-k
Plug-in Modules	Electrical Fuse , Inductor, MiM capacitor, MOS & PN varactor, Resistors, Deep Nwell, Zero Vt, Bipolar

GLOBALFOUNDRIES offers the 65nm process family complete with multiple Vt and multiple IO options. The 65nm process is ideal for graphics processors, network processors and other high performance applications. To address the need for low-leakage, low-power handheld and mobile applications, GLOBALFOUNDRIES offers the 65 Low Power enhanced (LPe) solution. Based upon a rotated substrate, it has been optimized to reduce leakage while still offering the performance necessary for most feature rich mobile products. Customers can also use the GlobalShuttle Multi-Project Wafer (MPW) program for prototyping and silicon validation of key IP blocks. GlobalShuttle offers MPWs for both the G and LPe processes. GlobalShuttle schedule is available here.

Common Design Platform

A key value proposition of the 65nm Common Platform Technology is the cross-foundry design enablement program that provides a comprehensive set of open, standard design solutions. Comprising of pre-qualified library, EDA, IP and other design service providers, the 65nm common design platform ensures GDSII compatibility for true multiple sourcing at GLOBALFOUNDRIES and its platform partners. It frees customers from proprietary lock-in as well as reduces risks and design costs associated with advanced nanotechnologies.

Design Enablement	65nm Generic	65nm Low Power Enhanced
Standard Cells (multi-Vt)	•	•
Memory Compilers (multi-Vt)	•	•
SP SRAM Compiler	•	•
DP SRAM Compiler	•	•
1P, 2P Register File	•	•
ROM	•	•
IO libraries	•	•
Analog Mixed Signal IPs	•	•
Standards Interface IPs	•	•
Tech files (LVS, DRC, PEX)	•	•
PDK	•	•
Design Reference Flow	•	•

65nm Logic Process

Process Features

Common Design Platform

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