Issue: Winter 2011

20nm Challenges and Solutions

By Wei Lii Tan, Sr. Product Manager, Cadence Design Systems

As the semiconductor industry continues its forward charge toward developing smaller, more powerful devices, advancements in process technology continue to provide significant improvements in chip power, performance, and area. 20nm technology is nearing production readiness in many aspects, and not a moment too soon. A whole category of mobile, connected devices awaits new technological advancements that can only be achieved by a combination of the right design talent and knowledge, an effective design methodology, and an advanced process technology.

Although 20nm process technology offers many advantages in terms of power, performance and area, not all semiconductor design companies will be adopting 20nm immediately. Typically the methodology ramp-up time for migrating to new process nodes is 6 to 18 months, and this holds true for 20nm too. Currently, the most visible design challenges at 20nm are adapting to double patterning requirements and new process rules specific to 20nm. Beyond that, increased wire delay and more susceptibility to on-chip variations or process variations make design closure a bit more complex at 20nm. Finally, one of the main reasons for moving to smaller process nodes is because designers want to take advantage of the increased logic density and be able to fit more logic on a single die; therefore the design methodology also needs to be able to support this increase in logic count.

Increased timing complexity and design size have always been challenges faced when migrating to newer process nodes – however, the introduction of double patterning requirements and related design rules are new manufacturing complexities that apply to 20nm and smaller geometries, which is why this challenge is almost always the foremost priority during 20nm ramp-up.

What is double patterning? Simply put, double patterning is a technique used at 20nm and smaller technology nodes to overcome lithography limits of semiconductor manufacturing. 20nm process technology is capable of supporting metal pitches that are smaller than traditional manufacturing equipment is able to support due to lithography limitations. Using double patterning overcomes lithography limitations to fully realize the potential of a 20nm process by manufacturing alternate tracks of metal in two separate steps. Double patterning requires extra masks, along with a colorized layout decomposition process to determine how layout features will be mapped to masks. However, double patterning is primarily needed for lower metal layers, and is not required for every layer.

Due to new design rules and double patterning requirements, it is important that process technology, library and IP development, as well as digital methodology at 20nm go hand-in-hand to achieve optimal results. Cadence's 20nm solution, for example, includes 20nm custom IP creation capabilities in Virtuoso, followed by a 20nm digital methodology using Encounter Digital Implementation System for implementation, and a 20nm electrical and physical signoff technology in Encounter Timing System, Encounter Power System and Physical Verification System. Applying each of these capabilities to a digital methodology provides a comprehensive and effective solution for 20nm.

Since double patterning involves manufacturing metal layers in separate steps, there is a slight area impact associated with this technique. With the correct methodology, however, this area impact can be minimized. By taking into account potential double patterning color conflicts during the placement stage, it is possible to reduce the area impact to a few percent (depending on the original utilization of the design). This means the placement engine should be able to either read double patterning information embedded in the standard cells and macros or "colorize" the standard cells on-the-fly to produce a placement that is double patterning correct - meaning pins of standard cells are not conflicting in terms of colors.

Next, during routing, a correct-by-construction approach is the preferred method. This means instead of treating DRC and double patterning checks as a post-processing procedure, DRC and double patterning color conflicts must be taken into account during the initial routing pass. Physical verification must be integrated within the router to realize this. DRC correctness during routing has been utilized for years, at older process nodes, but integrating double-patterning conflict checks during routing is new for 20nm. Together, double patterning-aware placement and routing can minimize the area impact of double patterning, leading to a more efficient die size.

During signoff, a few new considerations must be realized for 20nm. One of them is the fact that due to the usage of different masks, there usually is a slight offset between masks, since these won't be perfectly in alignment. Capacitance calculations that affect timing must be able to model these slight variations. Employing retargeting during RC extraction is a way to address this. The slight variations due to multiple masks is then modeled using a set of values in the resulting RC extraction results. Today, the SPEF (Standard Parasitic Exchange Format) format for RC values already supports this variation through multi-value SPEF, in which the capacitance for each node is described not only by a single number, but by a trio of minimum, typical, and maximum values.

These multi-value capacitance numbers are then utilized by timing and power signoff tools such as the Cadence Encounter Timing System and Encounter Power System. 20nm electrical signoff, coupled with physical signoff that checks not only for DRC-cleanliness but also for any remaining double patterning color conflicts, wraps up the digital signoff process for 20nm.

Having an effective, comprehensive 20nm-capable digital methodology is the key to removing the burden of new process rule and double patterning requirements from designers as much as possible with intelligent automation, allowing designers to focus on the real design and implementation aspects of producing a stellar design. With the new enhancements mentioned above, the Cadence 20nm solution delivers a robust methodology, enabling the creation of smaller and more powerful 20nm designs that will power the next generation of consumer devices.