GTC Santa Clara Agenda
Driving Innovation through True Collaboration

CEO Panel: "Design Enablement Challenges and Future Solutions"
ARM, Cadence, Mentor Graphics, Synopsys

Pundits have long predicted the convergence of computing, communications, consumer technologies. Today's converged electronic devices are faster, smaller, cheaper, always available, un-tethered, and support interactive data-rich applications often existing in a cloud. The actual convergence realization has greatly exceeded what the early pundits predicted thanks to highly synergized, multi-dimensional support ecosystems supporting the utilization and optimization of the billions of transistors that the leading edge process technologies provide. Harnessing the potential of the process technology enables new applications and products that are able to reach the markets and reach volume production quickly and cost effectively satisfying the global demand for consumer mobile applications.

The following executive panelists will address questions about the role of collaboration in developing design solutions for the leading edge process technology and the exciting product potential these new technologies unleash.

PANELISTS
Moderated by: Mojy Chian, Sr. VP Design Enablement, GLOBALFOUNDRIES

• Warren East, CEO ARM
• Lip-Bu Tan, CEO, Cadence
• Robert Hum, VP and GM, Mentor Graphics
• Aart de Geus, CEO, Synopsys

Track 1: ARM

PANEL: "Time For a Mainstream Revolution?"

PANELISTS
Moderated by: Ed Sperling, System-Level Design

• John Heinlein, VP Marketing - PIPD, ARM
• Walter Ng, VP IP Ecosystem, GLOBALFOUNDRIES
• Vishal Kapoor, VP Marketing - SoC Realization, Cadence
• Naveed Sherwani, CEO, Open-Silicon

ABSTRACT
Why is there so much activity at older process nodes? Moore's Law has always driven advances in process technology to the most advanced nodes, but advances in technology are now flowing in reverse. This panel will seek to answer some questions that are critical to everyone in the SoC supply chain:

• Why is it so important to retrofit the older process nodes?
• What impact will this have on stacking of die?
• What will happen to IP developed for older technology?
• How will this affect existing and new design tools?

Track 2: Cadence

"Cadence-GLOBALFOUNDRIES Collaboration Results in Designer Productivity"

PRESENTERS

• Wei Lii Tan, Sr. Product Marketing Manager, Cadence
• Steven Lewis, Product Marketing Director, Cadence
• Manoj Chacko, Product Marketing Director, Cadence

ABSTRACT
After a decade of collaboration, GLOBALFOUNDRIES semiconductor manufacturing technologies and Cadence EDA products continue to deliver industry-leading solutions to mutual customers. Attend the Cadence Platinum Partner presentation track to hear about our jointly developed production-ready reference flows (28SLP Digital/SoC Design Methodology, 28SLP Analog/Mixed-Signal Design Methodology) and to learn about "Getting What You're Entitled to with In-Design DFM."

Track 3: Mentor Graphics

"A New Method to Accelerate the Yield Ramp"

PRESENTERS

• Geir Eide Product Marketing Manager, Silicon Learning Products, Mentor Graphics
• Dr. Cornelia Horstmann, Manager, Product Marketing, GLOBALFOUNDRIES

ABSTRACT
Delivering a correct, high yielding product on time becomes more and more difficult at each node due to the increasing potential for systematic, design specific defects. This session shows how to increase IC yield using statistical analysis of volume test diagnosis data in a way that augments traditional solutions. The methodology, which relies on accurate single-die diagnosis of scan test failures, gives engineers a proven, very fast, and highly effective new way of defect localization and identification. This approach can also be the foundation for a collaborative process between fabless and foundry customers, benefiting both sides.

Track 4: Synopsys

"Addressing Physical Implementation Challenges at 20nm"

PRESENTER
JC Lin, VP of Engineering, Implementation Group, Synopsys

JC has been with Synopsys for more than 15 years working on various technologies, including RTL Synthesis and Physical Synthesis. Currently, JC leads the placement and clock tree synthesis (CTS) teams for IC Compiler. He holds a Ph.D. degree in Computer Science from State University at New York (SUNY) at Stony Brook.

ABSTRACT
GLOBALFOUNDRIES and Synopsys have partnered on complete design enablement for leading edge technologies including tool, IP, and flow enablement. One of the biggest new challenges confronting our industry at 20nm is the requirement for double patterning (DPT), since single mask exposure for lithography has hit its limit. This imposes new and stricter constraints on placement, routing, physical verification and parasitic extraction. As industry leaders in IC design and manufacturing race to prepare for 20nm technology, Synopsys, GLOBALFOUNDRIES and mutual customers are collaborating to provide one of the most efficient DPT-ready physical implementation solutions using IC Compiler, IC Validator and StarRC. These 20nm challenges and Synopsys' physical implementation solution are presented.

Track 5: Channel Partners

• MOSIS
• Open-Silicon
• Socle
• VeriSilicon