Synopsys Reference Flow

Overview

With close collaboration with Synopsys, GLOBALFOUNDRIES and the rest of the Common Platform partners have enabled Synopsys reference flow that addresses the design complexities of the leading edge processes. The reference flow provides a complete RTL-to-GDSII solution. The reference flow is available to GLOBALFOUNDRIES and Synopsys customers at no charge.

Complete RTL-to-GDSII Design Flow

Production-ready design flow derived from Synopsys' Pilot Design Environment using the Galaxy Design Platform
Created by Synopsys and validated by GLOBALFOUNDRIES, IBM and Samsung
Extensive testing with ARM libraries through Hercules™ DRC checks
Integrated DFM solution using IC Compiler
Consulting services available for customization

Comprehensive, Flexible Solution

The Synopsys Reference Flow is a comprehensive, production-ready design flow derived from Synopsys' Pilot Design Environment using the Galaxy™ Design Platform. The Reference Flow helps design teams transform RTL into GDSII that can be manufactured at GLOBALFOUNDRIES. It is delivered with source scripts, allowing design teams to modify and extend the flow to best address their project-specific needs.

The Reference Flow provides a fully hierarchical RTL-to-GDSII implementation flow consisting of modular and configurable steps for:

Technology Library Preparation
Synthesis
Design-for-test
Design Planning
Place and Route
Chip Finishing

Built-in analysis and sign-off support is provided through static timing analysis (STA), formal verification, automatic test pattern generation (ATPG), and power, rail and EM/IR analysis. Timing, signal integrity, test coverage, manufacturability and power are accounted for in each step in the design flow.

Fast Track to Silicon Innovation

The Synopsys Reference Flow can be quickly adopted by project teams, allowing them to focus on their design objectives rather than flow-related tasks. Key features of the reference flow include:

A complete RTL to sign-off flow using the full suite of production-proven Galaxy™ tools. The basis of the Common Platform Reference Design Flow has been proven through numerous tapeouts.
A complete, modular RTL-to-GDSII design flow is implemented using TCL and Perl scripts. The scripts are provided as source code, allowing designers to enhance and extend the basic flow to customize it for their specific design.
A Perl-based technology file preparation utility is provided to create a clean and complete set of technology files for use in the layout, extraction and physical verification steps.
An open, formal data structure provides consistent organization of technology and design related data. This structure facilitates multi-user, multi-site collaboration.
Flow execution is controlled using supplied makefiles to provide robust error checking, designer-level control, and visibility of flow execution.
Support for popular commercial and free-ware revision control software.
User documentation
A sample design shows designers how to use each step of the flow.

Silicon-Proven Flow

The Common Platform Reference Flow is derived from the Synopsys Pilot Design Environment and customized and tested with the Common Platform process technology and libraries. The Pilot Design Environment has been developed and used by Synopsys Professional Services and has been deployed to customers to create dozens of designs in a wide range of applications and process technologies.

Availability

The Synopsys Common Platform Reference Flow is available today. Synopsys customers using the Common Platform can request the Reference Flow using an on-line form available on Synopsys' SolvNet web site. The Reference Flow is delivered with the full set of scripts and associated documentation.

Available Services

Consulting services for the Reference Flow are available from Synopsys Professional Services. These services include customizing the Reference Flow to meet specific customer requirements as well as design services for deploying the flow on a chip project.