| IP Provider | Technology | Process | Description |
| ARM | 65 nm | LP | High Density Single Port SRAM Compiler |
| ARM | 65 nm | LP | High Density Dual Port SRAM Compiler |
| ARM | 65 nm | G | High Speed Single-Port SRAM Compiler |
| ARM | 65 nm | G | High Speed Dual-Port SRAM Compiler |
| ARM | 65 nm | LPe | High Speed Dual-Port SRAM Compiler |
| ARM | 65 nm | LPe | High Density Via Programmable ROM Compiler |
| ARM | 65 nm | LPe | Ultra High Density Two-Port Register Compiler |
| ARM | 65 nm | LPe | High Density Single Port SRAM Compiler |
| ARM | 65 nm | LPe | High Speed Single-Port SRAM Compiler |
| ARM | 65 nm | LPe | High Density Dual-Port SRAM Compiler |
| ARM | 65 nm | LPe | High Density Two Port Register Compiler |
| ARM | 65 nm | LPe | High Speed Single-Port Register Compiler |
| ARM | 65 nm | LPe | Fast Cache Instances for ARM Cores |
|