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Innopower

About Innopower

Innopower is a leading semiconductor IP provider with a very experienced engineering team with a history supporting very high-volume production. These IP products are highly differentiated and are in use by many foundries, IDM's and fabless design companies. The product offering focuses on the fundamental libraries (standard cells, memory compilers and I/O's) which are feature-rich and innovative. In addition, the broad product portfolio includes other IP's, such as special I/O and standard interface IPs. With the breath of its offering and competitive specifications, Innopower is there to support any SOC designs, whether the application is in consumer electronics, computers or communications.



Innopower and GLOBALFOUNDRIES

Innopower and GLOBALFOUNDRIES have established their partnership on a broad range of processes. Using GLOBALFOUNDRIES' advanced process technology, Innopower has implemented a variety of fundamental IP blocks, including cell libraries, memory compilers, and high speed I/O IPs. These IP blocks are ready to be integrated into your designs and deliver fast time-to-market to your product. The families of Innopower IPs are ready to be implemented in a broad range of applications including:

  • Mobile devices
  • Wireless devices
  • High-definition video player
  • Multi-media players, connected TV, STB
  • Ccommunication systems

We are confident that GLOBALFOUNDRIES customers will benefit from the low-power and area-efficient IP solutions. Innopower's solid track records of high reliable IPs and the excellent customer support were key factors in GLOBALFOUNDRIES 's decision to choose Innopower as their IP partner.



Innopower IPs are designed to address customers' growing needs of cost, power and performance requirements. The solid implementation of our IP solutions assure our customers to deliver the high quality, low-power and area-efficient IP products. We look forward to helping our customers in a broad range of markets to meet the tight time-to-market requirements!



Featured Products General Purpose I/O Library in 55nm LPe

This I/O library is designed with the GLOBALFOUNDRIES 55 nm LPe process. All I/Os are equipped with a rich selection of programmable features capable of adapting to a wide variety of application environments. Two layout structures, both optimized for pad limited and core limited designs, are available to support each programmable feature or function.

Single-Port-SRAM Memory Compiler in 55nm LPe


Innopower provides the synchronous high-density Single-Port-SRAM (SP-SRAM) as the SH-type compiler. The single-port SRAM can be incorporated with the Innopower standard cell library. Different combinations of number of words, bit widths, and aspect ratios can be used to generate the most desirable configurations. The Innopower SP-SRAM compiler supports optional row redundancy.

Dual-Port-SRAM Memory Compiler in 55nm LPe

Innopower provides the synchronous high-density Dual-Port-SRAM (DP-SRAM) as the SJ-type compiler. The DP-SRAM can be incorporated with the Innopower standard cell library. Different combinations of number of words, bit widths, and aspect ratios can be used to generate the most desirable configurations. The DP-SRAM can support to read and to write the same address in one cycle, the option of row-redundancy and a BIST interface option.

Single-port Register File Memory Compiler in 55nm LPe

Innopower provides the synchronous single-port register file (1PRF) as the SY-type compiler. Different combinations of number of words, bit widths, and aspect ratios can be used to generate the most desirable configurations. The 1PRF is suitable for the high speed but relatively small configurations  such as CPUs, high-speed data buffers, and communications.

Via1 Programmable ROM� Memory Compiler in 55nm LPe

Innopower provides the synchronous Via1 Programmable ROM (Via-ROM) as the SP-type compiler. This ROM can be incorporated with the Innopower standard cell library. Different combinations of number of words, bit widths, and aspect ratios can be used to generate the most desirable configurations.

Two-Port Register File Memory Compiler in 55nm LPe

Innopower provides the synchronous two-port register file (2PRF) as the SZ-type compiler. The 2PRF can be incorporated with the Innopower standard cell library. Different combinations of number of words, bit widths, and aspect ratios can be used to generate the most desirable configurations. The 2PRF is designed for one read port and one write port. It is most suitable for the high-speed applications, such as caches, high-speed data queues, and communication applications.

USB 2.0 OTG PHY in 55nm LPe

This USB 2.0 OTG PHY IP is a Universal Serial Bus (USB) transceiver that provides a complete range of host and peripheral functions. It is fully compliant with the USB specifications version 2.0. In the high-speed mode, this device is capable of transmitting or receiving the data at the speed of 480 Mbps.


IP Status
  55nm
IO
Memory
Memory HD
Memory HS
PHY - USB

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