Register for our Technical Seminars

Cadence and GLOBALFOUNDRIES have collaborated on advanced technology nodes, including 20nm, to address all signoff challenges and ensure the success of our mutual customers--from early process definition to modeling and manufacturing signoff. This presentation examines extraction, timing/power signoff, DFM, and physical verification challenges, and highlights how both companies have collaborated to provide solutions.

Presenter: Hitendra Divecha, Product Manager, QRC Extraction, Cadence Design Systems

The increasing complexity of next generation design enablement has prompted manufacturers to optimize their processes. In response, GLOBALBFOUNDRIES, a leader in 28 nanometer (nm) and 20nm Process Design Kits (PDKs), has developed an extensive library of advanced PDKs that incorporate current 28/20 nm leading edge technology.

Presenter: Maq Mannan, GLOBALFOUNDRIES

With increased demand for high performance in low-power or thermally constrained, cost-sensitive devices, more designers are turning to the ARM® Cortex™-A9 processor. Optimized for mobile, networking and enterprise applications, the energy-efficient ARM® Processor Optimization Pack™ (POP) solution for Cortex-A9 processors delivers a performance range from 1GHz to 1.6GHz for worst case conditions, with up to 2GHz in typical conditions. Learn how the POP will enable ARM Partners to quickly close timing of A9 implementations across a broad envelope of power, performance and area optimization points, while reducing risk and improving time to market.

Presenter: ARM

GLOBALFOUNDRIES will describe the methodology and collateral available in the GLOBALFOUNDRIES Production AMS flow. This flow is silicon validated. The presentation will describe how the IP design is captured in the collateral available from GLOBALFOUNDRIES. The results of silicon testing will be presented and guidelines to successful AMS design for GLOBALFOUNDRIES processes. The presentation will emphasize the 28nm design node but will also present the 20nm variant.

Presenter: Pei Yao, Senior Member of Technical Staff, GLOBALFOUNDRIES

Wireless communication is ubiquitous in our lives and prevalent in numerous applications that we take for granted to access information wherever we are. For example, internet access over WiFi is getting more and more widespread in homes, businesses and hot spots. To increase capacity and to address new applications, the underlying WiFi standards are evolving into new versions of the IEEE802.11x family, where IEEE802.11p is one of the latest amendments.

Presenter: Mats Carlsson, Operations Manager, Catena

The need for DFM is greater than ever. Litho sign off simulation is mandatory at every foundry for 40nm and below. Advanced fill is the next big challenge at leading edge nodes. Mentor’s Calibre DFM solution is ready today to address these and other requirements for 20nm ICs. Come and see the status and roadmap of industry-leading litho friendly design (LFD) and SmartFill technologies, and how you can use them in your design flows.

Presenter: Jean-Marie Brunet, Director Product Marketing for Model Based DFM and Place-and-Route Integration, Mentor Graphics Corporation

With GLOBALFOUNDRIES recently announcing a key milestone in our HKMG volume production, shipping in excess of 250,000 wafers, we are making further progress in our 28nm and 20nm platforms. In this session, GLOBALFOUNDRIES will share key updates of our HKMG yield progress, silicon maturity updates, as well as the latest status of our total product solution, working in collaboration with our ecosystem partners. You will also get an update of our leading 20nm platform offering and we will show you why 20LPM is endorsed as the "most competitive and usable" 20nm solution today.

Presenter: Kelvin Low, Product Marketing, Leading Edge Technologies, GLOBALFOUNDRIES

Learn how GLOBALFOUNDRIES and Synopsys are collaborating to deliver a silicon-proven, high performance, low power production design solution based on Synopsys Galaxy Implementation Platform, DesignWare Interface IP, plus Yield Explorer automated volume diagnostics, all optimized for GLOBALFOUNDRIES 28nm and below leading edge technologies.  Special emphasis will be placed on how Yield Explorer helps close the loop between design and manufacturing as part of GLOBALFOUNDRIES’ Yield Management System, through faster identification and correction of systematic failure mechanisms.

Presenters:
Sagar A. Kekare, Group Manager, Product Marketing Manufacturing and Yield Management Solutions, Synopsys
Kelvin Low, Deputy Director, Product Marketing, Leading Edge Technologies, GLOBALFOUNDRIES

Learn how GLOBALFOUNDRIES and Synopsys are collaborating to deliver a silicon-proven, high performance, low power production design solution based on Synopsys Galaxy Implementation Platform, DesignWare Interface IP, plus Yield Explorer automated volume diagnostics, all optimized for GLOBALFOUNDRIES 28nm and below leading edge technologies.  Special emphasis will be placed on how Yield Explorer helps close the loop between design and manufacturing as part of GLOBALFOUNDRIES’ Yield Management System, through faster identification and correction of systematic failure mechanisms.

Presenters:
Sagar A. Kekare, Group Manager, Product Marketing Manufacturing and Yield Management Solutions, Synopsys
Kelvin Low, Deputy Director, Product Marketing, Leading Edge Technologies, GLOBALFOUNDRIES

With the advent of 20nm, IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SoCs. At the same time they also face a slew of new design challenges at 20nm that severely impact design performance, power and time to market. Challenges such as double patterning aware placement and routing, DFM, extraction and timing, larger design sizes, stringent low power requirements and process variations have a major impact on design performance and productivity. This session will highlight some of the key capabilities and differentiators that Olympus-SoC offers to address complex 20nm challenges, and also provides a sneak peak of the product roadmap.

Presenter: Arvind Narayanan, Product Marketing Manager Place and Route Product Line, Mentor Graphics Corporation

With GLOBALFOUNDRIES recently announcing a key milestone in our HKMG volume production, shipping in excess of 250,000 wafers, we are making further progress in our 28nm and 20nm platforms. In this session, GLOBALFOUNDRIES will share key updates of our HKMG yield progress, silicon maturity updates, as well as the latest status of our total product solution, working in collaboration with our ecosystem partners. You will also get an update of our leading 20nm platform offering and we will show you why 20LPM is endorsed as the "most competitive and usable" 20nm solution today.

Presenter: Bob Chizmadia, CIC Methodology Services Director, Cadence Design Systems

GLOBALFOUNDRIES Seminar: GLOBALFOUNDRIES Digital Sign-Off Flow
GLOBALFOUNDRIES will describe the methodology and collateral available in the GLOBALFOUNDRIES SignOff Digital Flow. This flow comes in different variants for different technology nodes. It is silicon validated, is a fully executable flow and is designed to be modular and to provide quick setup for customers who wish to design to GLOBALFOUNDRIES process. It addresses critical design concerns and provides detailed and accessible methodology to address the challenges. The presentation will emphasize the 28nm and 20m variants of the flow.

Presenter: Steven Chan, GLOBALFOUNDRIES

In today's connected world, wireless applications have become an indispensible part of our lives. Around the globe, people are increasingly dependent on wireless communications and connectivity applications such as mobile phones, WiFi, Bluetooth, GPS, Mobile TV, Zigbee, UWB etc.
GLOBALFOUNDRIES gives its customers the edge to design innovative products for these applications via our advanced RFCMOS offering. This presentation will showcase how GLOBALFOUNDRIES has evolved its RFCMOS device offering and modeling solutions whilst highlighting its comprehensive EDA ecosystem, via true collaboration with partners, that enables Wireless SoC designs.

Verification of 20nm designs is expected to bring significant challenges. A robust verification methodology that addresses circuit reliability is increasingly difficult. At 20nm, new devices that incorporate thin oxides are less robust and more subject to electrical overstress (EOS) failures. The increased use of mixed-signal and multi-voltage design techniques also increases the likelihood that transistors could be implemented in an incorrect voltage domain. Preventing long term electrical failure means IC designers should utilize new techniques to validate ESD structures, protect against EOS, manage multiple power domains, and carefully balance sensitive analog circuits. This session describes these challenges and how Calibre PERC can provide a comprehensive platform to address these problems.

Presenter: Carey Robertson, Director of Product Marketing for LVS and Extraction Products, Mentor Graphics Corporation

Making the wrong decision during architectural planning can be costly, having negative impact on budget, time to market, and performance. This session will review Cadence chip planning and estimation tools that help designers make appropriate decisions to optimize their chip designs and select the best available IP.

Presenter: Steve Thomson, Business Development Manager, Cadence Chip Planning Solutions Group, Cadence Design Systems

Apache Seminar: Power and Reliability Sign-Off for Advanced 28nm Low Power Process

Presenter: Arvind Shanmugavel, Director of Applications Engineering, Apache

20nm is on the cutting edge of advanced process technology. It offers better power, performance, and area compared to other process nodes. But to fully utilize these advantages, design teams must be up to speed on addressing the main 20nm challenges: double patterning and DFM/variation in layout; significantly larger design sizes; and leveraging the latest technology to maximize chip performance.

Presenter: Wei-Lii Tan, Sr. Product Manager, Cadence Design Systems

With a rich and advanced portfolio of IPs as infrastructure, Socle is to introduce its competitive performance of Cortex A9 platform running at GLOBALFOUNDRIES 40 LP and 28 SLP, with proven volume customer. Socle is now one of the few major players possessing mixed signal capability and 28nm ASIC implementation experience with volume production.

Allied with its largest shareholder GLOBALFOUNDRIES since 2009, Socle Technology Corporation has been the world's leading-edge provider of platform SoC solutions and IC design service, featuring low power and high efficiency for ARM-processor based applications. Socle serves your best gateway to GLOBALFOUNDRIES for design service and opens up your new opportunities in connected consumer and mobile computing markets.

Presenter: Mr. Stone Peng, CEO and President, Socle Technology Corporation

Wireless communication is ubiquitous in our lives and prevalent in numerous applications that we take for granted to access information wherever we are. For example, internet access over WiFi is getting more and more widespread in homes, businesses and hot spots. To increase capacity and to address new applications, the underlying WiFi standards are evolving into new versions of the IEEE802.11x family, where IEEE802.11p is one of the latest amendments. Products for these applications requires silicon technologies offering a combination of good devices for RF and Analog functions as well as small geometries for area and power efficient Digital signal processing. This presentation will showcase how Catena is adapting its silicon proven WiFi development platform for the new and demanding requirements of these upcoming WiFi standards. It will also be showed how Catena addresses specific customer requirements to be able to quickly reach volume production of advanced RF SoCs using the advanced technologies from GLOBALFOUNDRIES.

Presenter: Mats Carlsson, Operations Manager, Catena