Conference Presentations and GLOBALSOLUTIONS Events at DAC
Conference Presentations and Panels
| MONDAY, JUNE 4 |
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| TIME |
EVENT |
LOCATION |
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DESCRIPTION |
| 10:15AM |
Si2 Round-Up @DAC: Standards in Action |
Room 301
Moscone Center
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Summary: Standards have been proven to reduce cost of operations, drive greater process efficiencies and offer greater opportunities for start-up companies to infuse fresh technology in the design and manufacturing of IC's. Si2 standards have been targeted to resolve "pinch-points" in the overall semiconductor food-chain with a steadfast focus on rapid adoption of these standards.
Speakers:
Vito Dai - GLOBALFOUNDRIES, Sunnyvale, CA
Jim Culp - IBM Corp., Hopewell Junction, NY
S.W. Paek - Samsung, Yongin-city, Republic of Korea
Concetta Riccobene - LSI Corp., San Jose, CA
Cathy Rogers - Synopsys, Inc., Mountain View, CA
Riko Radojcic - Qualcomm, Inc., San Diego, CA
rif Rahman - Altera Corp., San Jose, CA
Aveek Sarkar - Apache Design, Inc. a subsidiary of ANSYS, Inc., San
Jose, CA
Keith Felton - Cadence Design Systems, Inc., San Jose, CA
Dusan Petranovic - Mentor Graphics Corp., San Jose, CA
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| 4:00PM-5:00PM |
Synopsys Seminar - Comprehensive Optimized Design Solution and Faster Yield Ramp for 28nm and Below |
Booth #303
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Learn how GLOBALFOUNDRIES and Synopsys are collaborating to deliver a silicon-proven, high performance, low power production design solution based on Synopsys Galaxy Implementation Platform, DesignWare Interface IP, plus Yield Explorer automated volume diagnostics, all optimized for GLOBALFOUNDRIES 28nm and below leading edge technologies. Special emphasis will be placed on how Yield Explorer helps close the loop between design and manufacturing as part of GLOBALFOUNDRIES' Yield Management System, through faster identification and correction of systematic failure mechanisms.
Presenters:
Sagar A. Kekare, Group Manager, Product Marketing Manufacturing and Yield Management Solutions, Synopsys
Kelvin Low, Deputy Director, Product Marketing, Leading Edge Technologies, GLOBALFOUNDRIES |
| TUESDAY, JUNE 5 |
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| TIME |
EVENT |
LOCATION |
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DESCRIPTION |
| 10:00AM-11:00AM |
Synopsys Seminar - Comprehensive Optimized Design Solution and Faster Yield Ramp for 28nm and Below |
Booth #303
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Learn how GLOBALFOUNDRIES and Synopsys are collaborating to deliver a silicon-proven, high performance, low power production design solution based on Synopsys Galaxy Implementation Platform, DesignWare Interface IP, plus Yield Explorer automated volume diagnostics, all optimized for GLOBALFOUNDRIES 28nm and below leading edge technologies. Special emphasis will be placed on how Yield Explorer helps close the loop between design and manufacturing as part of GLOBALFOUNDRIES' Yield Management System, through faster identification and correction of systematic failure mechanisms.
Presenters:
Sagar A. Kekare, Group Manager, Product Marketing Manufacturing and Yield Management Solutions, Synopsys
Kelvin Low, Deputy Director, Product Marketing, Leading Edge Technologies, GLOBALFOUNDRIES |
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| 11:30AM-12:15PM |
"Pavilion Panel:
Foundry, EDA and IP: Solve Time-to-Market Already!"
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Booth #310 |
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Summary: Designing billion+ transistor SoCs for 20nm and below in 22 months is not fast enough! Challenges include qualifying and integrating IP blocks, custom logic, and achieving design closure. This panel will discuss what foundry, IP and EDA vendors are doing to step up and finally deliver plug-and-play solutions. Moderator: Ron Wilson - Altera Corp., San Jose, CA.
Speakers:
Dr. Naveed Sherwani - Open-Silicon, Inc., Milpitas, CA,
Kevin Meyer - GLOBALFOUNDRIES, Milpitas, CA,
Dr. Naveed Sherwani - Open-Silicon, Inc., Milpitas, CA
|
| 12:30PM-1:30PM |
Session 2U.28 - Adoption of Static Timing Analysis with Advanced On-Chip Variation at 28nm |
Room 105: Exhibit Floor |
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Adoption of statistical static timing analysis (SSTA) in industry has been slow due to the complexities of model generation and standard cell library characterization. One promising alternative to SSTA is to perform traditional corner based STA but adjust gate delays based on a simple statistical analysis (AOCV) of the standard cells in a library. This paper describes for a 28nm process technology and library the methodology by which the benefits of AOCV may be evaluated, as well as the analysis and validation experiments that AOCV adopters need to perform before migrating from traditional STA to AOCV based STA.
Speaker: Steven C. Chan - GLOBALFOUNDRIES, Milpitas, CA
Authors: Steven C. Chan - GLOBALFOUNDRIES, Milpitas,
CA
Ning Jin - Univ. of California, Los Angeles, CA
Tze Haw Liew - GLOBALFOUNDRIES, Milpitas, CA
Adrian Au Yeung - GLOBALFOUNDRIES, Milpitas, CA
Karsten Matt - GLOBALFOUNDRIES, Milpitas, CA
|
| 4:00PM-6:00PM |
Session 4U: USER TRACK
Circuit Analysis and Optimization Accuracy 4U.2: Analysis of Parasitic Extraction for Advanced Nodes (28nm) |
Room 106 |
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Since the interconnect parasitics are dominating the delay at advanced nodes below 90nm and 3d effects are impacting the accuracy of rule based 2.5d parasitic extraction it is necessary to monitor the accuracy of the parasitic extraction. We describe the flow of establishing an accuracy analysis and filtering results which matter in electrical analysis. The applied accuracy limits and test cases are listed.
Speaker: Hendrik T. Mau - GLOBALFOUNDRIES, Dresden, Germany
Author: Hendrik T. Mau - GLOBALFOUNDRIES, Dresden, Germany |
| WEDNESDAY, JUNE 6 |
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| TIME |
EVENT |
LOCATION |
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DESCRIPTION |
| 11:30AM |
Enabling ARM IP through the 28nm POP |
ARM Booth #1414 |
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Speaker: Kelvin Low |
| 12:30PM-1:30PM |
Session 6U.25 – User Track Poster Session:
Understanding and Designing for Variation in GLOBALFOUNDRIES 28-nm Technology |
Room 105: Exhibit Floor |
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This work examines the design impact of process variation in GLOBALFOUNDRIES 28nm technology. Variation effects are compared between GLOBALFOUNDRIES� 28nm and 40nm technologies. Then a design example is discussed that demonstrates the application of Solid.
Speaker: Pei Yao - GLOBALFOUNDRIES, Milpitas, CA,
Authors: Pei Yao - GLOBALFOUNDRIES, Milpitas, CA
Richard Trihy - GLOBALFOUNDRIES, Milpitas, CA |
| 6:00PM-7:00PM |
Work-In-Progress:
55.47 – Layout Small-Angle Rotation and Shift for EUV Defect Mitigation |
Esplanade Foyer |
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Defect mitigation is crucial for EUV lithography. One option is to relocate patterns to avoid defects. However, when the defect number increases, only pattern shift on X-Y directions becomes insufficient, requiring a small rotation on the reticle holder for a third exploring dimension. In this paper, we present the first work to find the optimal shift and rotation for layout patterns on blanks. Compared to the straightforward method to check every pair of defect and feature at every possible relocation position, our proposed algorithm can significantly reduce the runtime complexity to be linear. The experimental results validate our advances.
Authors: Yunfei Deng - GLOBALFOUNDRIES, Milpitas, CA,
Pawitter Mangat - GLOBALFOUNDRIES, Malta, NY
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| THURSDAY, JUNE 7 |
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| TIME |
EVENT |
LOCATION |
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DESCRIPTION |
| 3:30PM-5:30PM |
Session 11U: User Track:
Clocks and Timing |
Room 303 |
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Complex clocking design and timing convergence continue to be top priorities in IC design. IBM, Samsung, and Juniper Networks showcase their approaches and successes in clock network design and timing analysis/convergence for advanced nodes. Presentations in this session include clock grid construction, clock mesh tuning, SSTA topics on pessimism removal and flexibility, and two convergence approaches for ECO routing and timing window reduction.
Chair: Srinivas Nori - GLOBALFOUNDRIES,Milpitas, CA |
GLOBALSOLUTIONS Events at DAC
| MONDAY, JUNE 4 |
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| TIME |
EVENT |
LOCATION |
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DESCRIPTION |
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| 10:15AM |
Si2 Round-Up @DAC: Standards in Action |
Room 301
Moscone Center
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Introduction/Quick Refresher on DRC+
Presenter: Vito Dai,
GLOBALFOUNDRIES |
| 10:30AM |
IP Talks |
Booth #1202 |
|
DAC 2012,
ChipEstimate.com will present the latest solutions from the leading IP
suppliers and foundries on the IP Talks! stage. Watch this space to see
the schedule of participating partners and plan your DAC 2012 agenda.
Also, be sure to join us in booth 1202 for hands-on demonstrations of IP
exploration and chip estimation, and discover how toestimate your next
chip's size, power, and cost.
Presenter: Tony Luk IP Business Manager - GLOBALFOUNDRIES |
| 2:00PM |
Mentor Hitchhiker's Guide to Multi-Patterning panel at DAC |
Mentor Booth #1530 |
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Beginning at
20nm, the challenges of lithographic imaging require the use of double
patterning. Does this mean designers will have to do twice as much work?
What about those pesky cycle design rule errors? How will we be able to
keep it all straight? And just what are EDA vendors and foundries doing
to make the designer's life bearable? The best place to get some
straight answers is from someone who has already done it successfully.
Come to this "talk show" format session to hear experts describe their
multi-patterning trials and tribulations, and zero in on the critical
factors that determine a successful outcome.
This is a one-time only,
limited seating event. Sign up today to reserve your spot.
Moderator: Ed Sperling, Editor-In-Chief, System Level Design
- Michael White, Director of Product Marketing Calibre PV, Mentor Graphics
- Rob Aiken, R&D Fellow, ARM
- Jean-Pierre Geronimi, Special Project Director in Central CAD and Design Solution, STMicro
- Kuang-Kuo Lin, Director, Foundry Design Enablement, Samsung
- Lars Liebmann, Distinguished Engineer, IBM
- Luigi Capodieci, Director DFM/CAD and R&D Fellow, GLOBALFOUNDRIES
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| TUESDAY, JUNE 5 |
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| TIME |
EVENT |
LOCATION |
|
DESCRIPTION |
| 7:15AM-8:25AM |
GLOBALFOUNDRIES, ARM, Samsung, Synopsys Breakfast:
Breaking Through Barriers: High Performance and Energy Efficient ARM
Powered® SoCs at 32/28nm and 20nm
Advance Registration Required |
Marriott Hotel
Golden Gate Ballroom |
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The demand for
higher performance and more power efficient processors in smartphones,
tablets and other mobile computing applications is driving companies to
move to advanced 32/28nm and 20nm process nodes.
Are you ready for 32/28nm and 20nm advanced nodes?
In this session, experts from Samsung, GLOBALFOUNDRIES, Synopsys and ARM
will describe key design and manufacturing challenges facing designers
at 32/28nm and 20nm and how, through collaboration, the companies are
addressing these challenges. The collaboration combines
semiconductor manufacturing, EDA and IP enablement, shared cycles
of learning and silicon proof points to enable a complete silicon proven
design enablement and manufacturing-ready solution for optimized
implementations of ARM Powered high performance and energy efficient
SoCs.
A live audience Q&A session and prize drawing will follow the
presentations
|
| 1:30PM |
IP Talks |
Booth #1202 |
|
DAC 2012,
ChipEstimate.com will present the latest solutions from the leading IP
suppliers and foundries on the IP Talks! stage. Watch this space to see
the schedule of participating partners and plan your DAC 2012 agenda.
Also, be sure to join us in booth 1202 for hands-on demonstrations of IP
exploration and chip estimation, and discover how toestimate your next
chip's size, power, and cost.
Presenter: Tony
Luk, IP Business Manager - GLOBALFOUNDRIES
|
| WEDNESDAY,JUNE 6 |
| TIME |
EVENT |
LOCATION |
|
DESCRIPTION |
| 8:00AM-9:00AM |
IBM, GLOBALFOUNDRIES, Samsung and Cadence Breakfast Panel:
The Path to Yielding at 2(x)nm and Beyond
Advance Registration Required |
270-276 (Moscone Convention Center) |
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At advanced
nodes there are disruptive design and manufacturing discontinuities that
must be understood and handled to ensure successful silicon yields.
Moving to these technologies calls for a paradigm shift in the
way Ics are designed and manufactured.
This panel explores the challenges of process and IC design at
advanced nodes, and ramping to production.
We examine these challenges from the foundry, EDA, and customer
perspectives and share our combined experiences and recommendations on
how to ensure a solid path to yielding at 2(x)nm and beyond.
Moderator:
Steve Leibson Panel
Members:
Gary Patton, VP, Semiconductor R&D - IBM
Mojy Chian, SVP Design Enablement - GLOBALFOUNDRIES
K.M. Choi, VP IDC - Samsung
Chi-Ping Hsu, SVP R&D - Cadence Design Systems
|
| 11:30AM |
GLOBALFOUNDRIES' Presentation in ARM Connected Community: Pavilion
|
Booth #802 |
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ARM Connected
Community Pavilion Booth 802 |
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3:30PM |
IP Talks |
Booth #1202 |
|
DAC 2012,
ChipEstimate.com will present the latest solutions from the leading IP
suppliers and foundries on the IP Talks! stage. Watch this space to see
the schedule of participating partners and plan your DAC 2012 agenda.
Also, be sure to join us in booth 1202 for hands-on demonstrations of IP
exploration and chip estimation, and discover how toestimate your next
chip's size, power, and cost.
Presenter: Thomas Wong - GLOBALFOUNDRIES
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